The present invention relates generally to non-volatile memories and in particular the present invention relates to erase operations in a non-volatile memory device.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a flash memory. A flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
To program a memory cell, a high positive voltage Vg is applied to the control gate of the cell. In addition, a moderate positive voltage is applied to the drain (Vd) and the source voltage (Vs) and the substrate voltage (Vsub) are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell that has not been programmed.
In flash memories, blocks of memory cells are erased as in groups. This is achieved by putting a negative voltage on the wordlines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements. In an erased state, the memory cells can be activated using a lower control gate voltage.
A common problem with flash memory cells is over-erasure. A cell that is erased past a certain point becomes depleted and cannot be fully turned off. That is, too many electrons are removed from the floating gate, and the memory cell floating gate voltage becomes more positive than the threshold of the cell. The cell, therefore, cannot be turned off even if the control gate is at a ground potential. An over-erased memory cell can cause all memory cells coupled to the same column to be read as erased cells, even though they may be programmed.
In current flash memory cells, a pre-program cycle is performed on the block of memory cells prior to performing an erase cycle. As such, all the cells in a block are first programmed. The cells are then erased until all the cells are completely erased. A threshold voltage (Vt) distribution tightening operation is performed following the erase operation to recover memory cells that are over-erased. As flash memory devices increase in memory cell density, the time needed to perform a complete erase operation also increases.
In flash memories, a substantial part of the erase cycle time is spent on the erase cycle. Out of a typical 1-second erase operation; about one-half of the time is spent on pre-programming the memory cells, and the other half is used on the erase cycle. An erase pulse requires about 10 ms, while an erase verification operation requires less than 1 xcexcs. With the density of flash memories increasing, the total time to verify all the locations is becoming a substantial part of the cycle. For instance, in a 64 Megabit flash device organized in 16 erasable blocks, there are 4 million locations that need to be verified during an erase operation. A typical 1 xcexcs time for each verify cycle results in a verify time of 4 seconds. Further, memory cells are being verified for levels that are much tighter than their regular read levels. Thus, they need to be sensed much slower. For instance, a normal read is verifying that an erased cell has a threshold level (Vt) that is less than 4.5V. During erase verification, the memory verifies that the cell has a Vt that is less than 3V. This margin is smaller than prior memories and is more susceptible to noise.
Another common problem with flash memory devices is defects in the memory array that occur during manufacture of the array. Typical defects can include bad memory cells, open circuits, shorts between a pair of rows and shorts between a row and column. Defects can reduce the yield of the flash memory device. A way to resolve this problem, without discarding the memory device, is to incorporate redundant elements in the memory to selectively replace the defective elements. For example, redundant columns are a common form of redundant elements used in flash memory to replace defective primary columns (or defective cells coupled to the columns). The redundant columns are mapped to the defective columns by a redundant circuit. That is, a redundant circuit is used to selectively route address requests directed to a defective column to a redundant column. Redundant circuitry generally includes redundant registers used to store addresses of defective elements and a logic circuit used to compare address requests with addresses stored in the redundant registers. Typically, the redundant registers comprise electrical fuses, anti-fuses or non-volatile memory cells.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory with an improved process for erasing and verifying a memory that incorporates redundant columns.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device includes an array of erasable blocks of non-volatile memory cells. At least one of the blocks has at least one redundant column. A block register is used for each erasable block to store data to indicate when the erasable block is fully erased. A control circuit performs an erase verification on each erasable block and provides data to an associated block register based on an outcome of the erase verification. The control circuit performs the erase verification of the at least one redundant column in conjunction with the erasable block where the at least one redundant column resides.
In another embodiment, a non-volatile flash memory device includes an array of non-volatile memory cells arranged in erasable blocks. Each erasable block comprises multiple sub-blocks. At least one of the sub-blocks includes a redundant column to selectively replace a defective column in one of the sub-blocks. A sub-block register is used for each sub-block to store a bit that indicates when the associated sub-block is either in an erased state or needs further erase. A state machine is used to control memory operations. The state machine performs individual erase verification operations on each sub-block including any redundant columns physically located in the sub-block. The state machine also provides the bit to the associated sub-block register based on the outcome of the erase verification operation.
In another embodiment a non-volatile flash memory device includes an array of non-volatile memory cells arranged in erasable blocks. Each erasable block comprises multiple sub-blocks. At least one of the sub-blocks has multiple redundant columns to selectively replace defective columns in the sub-blocks. A sub-block register is used for each sub-block to store data to indicate when the associated sub-block is in an erased state. A control circuit is used to control memory operations. The control circuit performs individual erase verification operations on each sub-block in conjunction with any redundant columns physically located in the sub-block. In addition, the control circuit provides the data to the sub-block register based on the outcome of the erase verification operation on an associated sub-block.
In another embodiment a non-volatile memory device includes an array of erasable blocks of non-volatile memory cells. At least one of the blocks has at least one redundant column. Block registers are associated with the erasable blocks. Each of the block registers store a bit that indicates when the erasable block is fully erased. Address registers are also associated with the erasable blocks. Each of the address registers stores a start verification address for its associated erasable block. Control circuitry to perform erase verification on each block and provide data to the block registers in response to an outcome of the erase verification on an associated block. The control circuit starts an erase verification on each block at a start verification address of an associated address register. The control circuitry also performs the erase verification of the at least one redundant column in conjunction with the block where the at least one redundant column resides.
In another embodiment, a non-volatile flash memory system includes a processor and a memory. The processor is used to provide an erase command. The memory is coupled to the processor. The memory includes an array, a redundant circuit and a control circuit. The array includes non-volatile memory cells arranged in erasable blocks. Each erasable block comprises a plurality of sub-blocks. At least one of the sub-blocks has at least one redundant column. Each sub-block has an associated sub-block register to store a bit that indicates when the sub-block is fully erased. The redundant circuit is used to redirect address requests from a defective column in a sub-block to the at least one redundant column. The control circuit is used to control erase operations in response to the erase command from the processor. The control circuit disables the redundant circuit from redirecting address requests from a defective column in the sub-block to the at least one redundant column during an erase verification of an erase operation. The control circuit further provides data to the sub-block register during an erase verification of a sub-block associated with the sub-block register.
A method of performing an erase verify operation on an erasable block of flash memory cells comprises verifying a state of each memory cell physically located in the block and ignoring a state of memory cells coupled to redundant columns mapped to the block but not physically located within the block.
A method of erase verify of an erasable sub-block of non-volatile memory cells comprises reading each memory cell in a primary sub-block of the sub-block of memory cells, reading each memory cell coupled to redundant columns physically located in the sub-block of memory cells, when all the memory cells are in an erased state, storing a bit in a sub-block register that indicates the sub-block is in an erased state, when a memory cell is read that is not in an erased state, storing the bit in a sub-block register that indicates the sub-block needs further erasure.
A method of operating a flash memory comprises applying an erase pulse to an array of non-volatile memory cells arranged in erasable sub-blocks having redundant columns, verifying each sub-block to determine if the memory cells located in each sub-block are in an erased state, wherein verification of each sub-block includes verification of memory cells coupled to redundant columns physically located in the sub-block and ignoring memory cells coupled to redundant columns mapped to the sub-block but located in another sub-block, storing data in sub-block registers associated with each sub-block, wherein the bit stored in the sub-block register indicates whether the memory cells in an associated sub-block are in an erased state, reading the bit in each sub-block register and applying further erase pulses to sub-blocks having a sub-block register with a bit that indicates the sub-block needs further erase.
A method of erasing a flash memory comprises performing a pre-program operation on a block of memory cells, applying an erase pulse to the block of memory cells, performing a first erase verification operation on a first sub-block of the block of memory cells and on redundant columns physically located in the first sub-block and terminating the erase verification of the first sub-block.
A method of performing an erase operation on a non-volatile memory comprises applying a first erase pulse to a block of memory cells, sequentially reading memory cells of a first sub-block of the block of memory cells, wherein the first sub-block includes memory cells coupled to redundant columns physically located in the first sub-block, ignoring memory cells coupled to redundant columns mapped to the first-sub block but not physically located in the first sub-block, storing an address of a first memory cell that is determined to be programmed in an address register, applying a second erase pulse to the first sub-block of memory cells and performing a second sequential reading of memory cells of the first sub-block starting at the first memory cell address.